The present invention relates to a multi-layer ceramic capacitor including side margins provided in a subsequent step, and to a method of producing the multi-layer ceramic capacitor.
Along with miniaturization and achievement of high performance of electronic devices, there have recently been increasingly strong demands for increase in capacitance and the like with respect to multi-layer ceramic capacitors used in the electronic devices. In order to meet those demands, for example, it is effective to enlarge an intersectional area of internal electrodes of the multi-layer ceramic capacitor as much as possible.
In order to enlarge the intersectional area of the internal electrodes, the following technique is effective: side margins for ensuring insulation properties of the periphery of the internal electrodes are provided to a multi-layer chip in a subsequent step, the internal electrodes being exposed to the side surfaces of the multi-layer chip. This technique makes it possible to form thin side margins and relatively increase the intersectional area of the internal electrodes.
Meanwhile, in the multi-layer ceramic capacitor that is provided with the side margins in a subsequent step on the side surfaces of the multi-layer chip, foreign substances derived from the internal electrodes and the like may adhere to the side surfaces of the multi-layer chip in the production process. For those reasons, the internal electrodes may be electrically conducted to each other and a short circuit failure between the internal electrodes may occur in the side surfaces of the multi-layer chip.
To cope with this drawback, for example, as in the invention disclosed in Japanese Patent Application Laid-open No. 2009-016796, oxidized areas having low electrical conductivity can be formed at the ends of internal electrodes to inhibit a short circuit failure between the internal electrodes in the side surfaces of a multi-layer chip.